1. Field of the Invention
The present invention relates to nonvolatile semiconductor memory, and more particularly to providing row redundancy in nonvolatile semiconductor memory.
2. Description of the Related Art
Nonvolatile semiconductor memory array retains stored data when power is removed. Many different types of nonvolatile data cells suitable for nonvolatile memory are known, including a class of single transistor devices that are based on the storage of charge in discrete trapping centers of a dielectric layer of the structure, and another class of devices that are based on the storage of charge on a conducting or semiconducting layer that is completely surrounded by a dielectric, typically an oxide. Techniques are also known for achieving multiple bit storage in a single transistor nonvolatile data cell by programming the multiple bits into a data cell as different voltage levels or in different parts of the cell. The trapped charge establishes the threshold voltage, or VT, of the device, which is sensed when the memory is read to determine the data stored therein.
An illustrative well known type of compact floating gate data cell structure is the stacked gate structure. A floating gate, typically a doped polysilicon layer, is sandwiched between two insulator layers, typically oxide. The top layer of the stack is a control gate electrode, typically a doped polysilicon layer. In one type of floating gate transistor, the stacked gate structure overlies part of a heavily doped n+ source region and a heavily doped n+ drain region, as well as a channel region between the source region and the drain region. The channel region is part of a p-well, which also contains the source region, the drain region, and a heavily p+ doped contact region. The p-well typically is contained within an n-type substrate or within an n-well, which also contains a heavily n+ doped contact region. The n-well is in turn contained in the p-type substrate. Many variations in the floating gate data cell structure are known, and include asymmetrical stacked gate structures, split gate structures, and so forth. Moreover, although the structure described herein is an n-channel enhancement mode device, nonvolatile data cells may be fabricated as either n-channel or p-channel devices or as enhancement or depletion mode devices.
As is typical of nonvolatile data cells that are capable of being repeatedly programmed and erased, the various functions of the stacked gate data cell are controlled by applying various bias voltages. The voltage applied to the control gate is VG, the voltage applied to the source is VS, the voltage applied to the drain is VD, the voltage applied to the p-well is VP, the voltage applied to the n-well is VN, and the voltage applied to the p-type substrate is VB. Typically the substrate is grounded, i.e. VB=0V. Typically writing or programming the data cell means adding negative charge to the floating gate while erasing the data cell means removing negative charge from the floating gate, but the charged state can be considered the erased state if desired. Other voltages are applied to read the charge state of the data cell by detecting the threshold voltage VT of the data cell, which ideally is done without disturbing the charge state.
Depending to some extent on device characteristics, stacked gate transistors may be programmed by moving electrons to the floating gate using Fowler-Nordheim (xe2x80x9cFNxe2x80x9d) tunneling or electron injection. Electron injection typically is done using channel hot electron injection (xe2x80x9cCHExe2x80x9d) or channel-initiated secondary electron injection (xe2x80x9cCISEIxe2x80x9d). FN tunneling remains a popular choice in flash memory for erase operations.
A typical semiconductor memory contains millions of data cells. To avoid requiring that every one of the millions of data cells and associated connective structures in a non-volatile semiconductor memory device be error free and perfect, memory devices such as NOR-type flash memories often use redundant rows to repair bad rows. In one type of flash memory that supports sector erase, for example, a sector contains 512,000 bits of regular data cells (256 rows by 2K columns) and 32,000 bits of redundant cells (16 redundant rows by 2K columns.
During operation, conventional flash memories may be erased sector-by-sector using an embedded Sector Erase. However, if the data cells in the sector start out at different threshold voltages and only a sector erase operation is performed, some of the data cells may be erased near to or into depletion which will cause data errors in NOR-type flash memory products. To avoid this problem, a common practice for the embedded Sector Erase is to use a number of other operations in addition to the Sector Erase operation to prevent any of the data cells from being depleted.
The additional operations in common use for an embedded sector erase are Preprogram, Pre-Program Verify, Erase Verify (following the Erase operation), Post-Program Verify, and Post-Program. The first set of operations typically is a Pre-program followed by a Preprogram Verify. The objective of the Preprogram and Preprogram Verify operations is to program all of the cells in the selected sector, including the redundant cells, to a high VT, illustratively VT=5 volts, so that all of the cells can be erased from the same state. Both the Preprogram and Preprogram Verify operations are normally byte wide. The second set of operations typically is Erase followed by Erase Verify. All of the data cells including the redundant data cells in the selected sector are erased to a low VT, illustratively VT less than 3 volts. Erase is normally a bulk operation, and Erase Verify is normally a byte wide operation. The third set of operations typically is a Post-Program Verify followed by a Post-Program. All the cells including the redundant cells in the selected sector that fail Post-Program Verify, which occurs when they are erased too much (illustratively VT less than 0.5 volts), are Post-Programed and Post-Program Verified again so that all of the data cells in the selected sector have their threshold voltage VT in a range of from 0.5 volts to 3 volts, for example. The Post-Program Verify and Post-Program operations are normally byte wide operations. The Table of FIG. 1 shows illustrative bias conditions for a selected sector of a flash memory array that uses CHE for programming and FN for erase, during each of the operations in an embedded sector erase. In unselected sectors, all of the row lines, columns, sources and the bulk remain grounded during all operations.
First, for the Preprogram operation, the source and bulk, used in this embodiment to refer to the p-well in which the data cell is fabricated (typically contained within a higher biased n-well, which in turn is in a grounded substrate), are biased at 0 volts for all cells in the selected sector, the selected row is biased at 10 volts, and the selected columns (typically one byte) is biased at 5 volts. Hot electrons are injected into the floating gate of the floating gate transistors in the selected data cells, which raises their threshold voltage VT. A suitably high VT value is VT=5 volts.
Next, for the Preprogram Verify operation, the source and bulk are biased at 0 volts for all cells in the selected sector, the selected row is biased at 6 volts, and the selected column is biased at 1 volt to sense the threshold voltage. If the threshold voltage is correct, no further programming of the particular data cell is performed. However, if the threshold voltage is not correct, the particular data cell is again Preprogrammed and Preprogram Verified until an acceptable threshold voltage is achieved.
Next, for the Erase operation, the source is floated, the bulk is biased at 6 volts for the selected sector, the rows of the selected sector are biased at minus 10 volts, and the columns of the selected sectors are floated. Electrons tunnel from the floating gates of the floating gate transistors in the selected data cells to the bulk, which lowers their threshold voltage VT. A suitably low VT value is VT less than 3 volts.
Next, for the Erase Verify operation, the source and bulk are biased at 0 volts for all cells in the selected sector, the selected row is biased at 4 volts, and the selected column is biased at 1 volt to sense the threshold voltage. If the threshold voltages of each of the cells is less than the highest allowable low VT value, no further erase is performed. Otherwise, the erase and erase verify operations are repeated until the threshold voltages of all cells are achieved or an error condition is reported.
Next, for the Post-Program Verify operation, the source and bulk are biased at 0 volts for all cells in the selected sector, the selected row is biased at 2.5 volts, and the selected column is biased at 1 volt to sense the threshold voltage. If the threshold voltage is greater than or equal to the lowest allowable low VT value, say a VT of 0.5 volts, no Post-Programming of the particular data cell is performed. However, if the threshold voltage is too low, the particular data cell is Post-Programmed.
Next, for the Post-Program operation, the source and bulk are biased at 0 volts for all cells in the selected sector, the selected row is biased at 5 volts, and the selected column is biased at 3 volts. Weak hot electron injection occurs into the floating gate of the floating gate transistors in the selected data cells, which minutely raises their threshold voltage VT. Post-Program and Post-Program Verify are repeated until an acceptable threshold voltage is achieved.
The foregoing technique for embedded sector erase is effective when redundant rows are used to replace a word line group having an individually defective row. However, the technique can be ineffective when two regular rows are shorted together. The problem arises when cells are being programmed in only one of two shorted rows. In this event, the selected row is biased at 10V and the unselected row is biased to 0V, but since the rows are physically shorted, a functional failure results.
Some of the various techniques for implementing row redundancy in nonvolatile memory, including techniques for handling shorted rows, are disclosed in U.S. Pat. No. 5,233,559, issued Aug. 3, 1993 to Brennan, Jr. and entitled xe2x80x9cRow Redundancy for Flash Memories,xe2x80x9d U.S. Pat. No. 5,347,489 issued Sep. 13, 1994 to Merchant et al. and entitled xe2x80x9cMethod and Circuitry for Preconditioning Shorted Rows in a Non Volatile Semiconductor Memory Incorporating Row Redundancy,xe2x80x9d U.S. Pat. No. 5,327,383 issued Jul. 5, 1994 to Merchant et al. and entitled xe2x80x9cMethod and Circuitry for Erasing a Nonvolatile Semiconductor Memory Incorporating Row Redundancy,xe2x80x9d and U.S. Pat. No. 6,301,152 issued Oct. 9, 2001 to Campardo et al. and entitled xe2x80x9cNon Volatile Memory Device With Row Redundancy.xe2x80x9d Despite these and other various techniques, a need remains for a row redundancy technique for flash memories that has low decoder and controller overhead and is nonetheless able to replace even two shorted rows.
One embodiment of the present invention is a method of operating a nonvolatile semiconductor memory in preparation for programming one or more data cells therein. The method comprises identifying a plurality of used rows and a plurality of unused rows of nonvolatile data cells within a common bulk region of the memory, at least some of the unused rows being either bad rows or redundant rows; preprogramming the data cells of the used rows; during the preprogramming step, establishing on the data cells of the unused rows a bias condition that tends to converge the data cells of the unused rows to a threshold voltage near a UV erased threshold; and erasing the data cells of the used rows.
Another embodiment of the present invention is a method of performing an embedded erase of nonvolatile semiconductor memory having a plurality of rows of data cells arranged in a plurality of sectors, wherein some of the rows of data cells within each sector are regular rows of data cells and some of the rows of data cells within each sector are redundant rows of data cells. The method comprises identifying a plurality of word line groups for use, within each of the sectors; identifying at least one word line group within each of the sectors for nonuse; selecting a sector; programming the data cells in the word line groups identified for use in the selected sector; biasing the rows of the word line group or groups identified for nonuse during the programming step so that the data cells thereof tend to converge to a threshold voltage near a UV erased threshold; erasing the data cells in the word line groups identified for use in the selected sector; and biasing the rows of the word line group or groups identified for nonuse during the erasing step so that the data cells thereof are not erased.
Another embodiment of the present invention is a nonvolatile semiconductor memory comprising a memory array having a plurality of rows of nonvolatile data cells arranged in a plurality of sectors, the rows of data cells having respective word lines; a plurality of word line drivers coupled to the word lines; a plurality of word line pre-drivers coupled to respective groups of the word line drivers; a sector pre-decoder coupled to the word line pre-drivers; a regular word line group pre-decoder coupled to the word line pre-drivers; a redundant word line group pre-decoder coupled to the word line drivers; a word line pre-decoder coupled to the word line pre-drivers; a redundant word line group selector coupled to the redundant word line group pre-decoder; and an X address line coupled to the sector pre-decoder, the regular word line group pre-decoder, the redundant word line group pre-decoder, the word line pre-decoder, and the redundant word line group selector.
Another embodiment of the present invention is a nonvolatile semiconductor memory comprising means for identifying a plurality of used rows and a plurality of unused rows of nonvolatile data cells within a common bulk region of the memory, at least some of the unused rows being either bad rows or redundant rows; means for preprogramming the data cells of the used rows; means for establishing on the data cells of the unused rows, in coordination with the preprogramming means, a bias condition that tends to converge the data cells of the unused rows to a threshold voltage near a UV erased threshold; and means for erasing the data cells of the used rows.